Christmas song

Nice song!! Christmas song by Michael Bubble


Enjoy!

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GD&T

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GD&T stands for Geometric Dimensioning and Tolerancing and is written in  ASME Y14.5-2009.  The GD&T is used often in creating detail 2D drawing and is very powerful tools to ensure that the product will be correctly manufactured.  See below for the most used GD&T symbols. 
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Photolithography

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The word lithography comes from the Greek  lithos , meaning stones, and  graphia , meaning to write. It means quite literally writing on stones. In the case of semiconductor lithography (also called photolithography) our stones are silicon wafers and our patterns are written with a light sensitive polymer called a photoresist. To build the complex structures that make up a transistor and the many wires that connect the millions of transistors of a circuit, lithography and etch pattern transfer steps are repeated at least 10 times, but more typically are done 20 to 30 times to make one circuit. Each pattern being printed on the wafer is aligned to the previously formed patterns and slowly the conductors, insulators, and selectively doped regions are built up to form the final device. [1] The steps used in photolithography is well described at following figures. [2] Intel has this nice simple way of description for the photolithography process in video....
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CLEANLINESS OF A CLEAN ROOM

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When people designing for a product that is going to be used in the clean room environment, one thing that must be put into consideration is how to let the product itself has a very little of contamination. This is very important because when the product attracts contamination, it will affecting the end product of chip production, i.e.: contaminating the wafer which resulting in defects thus yield lost. First of all, one might want to understand how the clean room being classified. So below (taken from wikipedia ), you may find that the cleanliness of a clean room is segmented into how many contamination accepted in an area. Normally the chip manufacturer will need to define the cleanliness of their fab by judging from the application they will use. The smaller the overlay , the cleaner they want to go.  For example, in 2007 there is a news , Intel aimed to produce a 45nm chips, for this, they came up with a clean room class 1 in about 184,000 square feet, meaning that...
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